1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and particularly to realization of a super miniaturized insulated gate field effect transistor with a larger current and a superhigh operation speed.
2. Description of the Related Art
Enhancement of performance of insulated gate field effect transistors constituting an ultrahigh-density integrated circuit device (hereinafter referred to simply as xe2x80x9cMOSxe2x80x9d) has been achieved by reducing transistor area and gate size so as to attain the merits of reduction in power supply voltage used and reduction in parasitic capacitance according to the scaling rule. At present, super miniaturized MOSs with a gate length of not more than 160 nm have also been put to practical use. In these super miniaturized MOSs, reduction of the source and drain junction depth has also been tried attending on the reduction in the gate length, and a shallow junction depth of not more than 30 nm has been attained at present. In reducing the source and drain junction depth, reduction of the resistance of a source diffusion layer is essential to realization of a large current while restraining the so-called short channel effect, namely, an abrupt lowering of threshold voltage attendant on the reduction of the gate length.
FIG. 2 is a sectional view schematically showing a conventional super miniaturized MOS, and FIG. 3 shows an impurity distribution in the depth direction in high concentration source and drain shallow junctions 4, 5 (called xe2x80x9cextensionxe2x80x9d) in FIG. 2. In FIG. 2, in the case of an N conductive type MOS, a gate insulation film 2 is provided on the surface of a P conductive type Si substrate 1, and a gate electrode 3 is provided thereon. N conductive type source and drain shallow junction diffusion layers 4, 5 and so-called pocket diffusion layer regions 7 which are high concentration P conductive type impurity diffusion layers for preventing the so-called short channel effect are introduced by using the gate electrode 3 as an implantation mask. Further, source and drain diffusion layers 9, 10 of N conductive type and deep junction are introduced by using a gate side wall insulation film 8 as an implantation mask. In the figure, numeral 11 denotes a silicide film, 12 a surface protective insulation film, 13 a source electrode, and 14 denotes a drain electrode.
The source and drain shallow junction diffusion layers are fabricated conventionally by the following steps. (1) A high concentration impurity is introduced by low acceleration energy ion implantation using the gate electrode as an implantation(screen) mask; (2) then, the pocket regions are provided by ion implantation; (3) further, the source and drain diffusion layers of deep junction are provided by ion implantation using the gate electrode side wall insulation film as a mask; and (4) thereafter, activation of the implanted ions is carried out by a high-temperature short-period annealing method. The short-period anneal is adopted in order to achieve the activation while retaining the steep impurity distribution obtained upon ion implantation, through minimizing the spreading of junction depth due to thermal diffusion of implanted impurities.
However, further reductions in the junction depth and the resistance of the diffusion layers cannot be achieved by only the short period annealing at high temperature. A principal reason is based on the so-called transient enhanced diffusion phenomenon, namely, enhanced diffusion under a relatively low temperature condition of not more than 900xc2x0 C. due to the presence of interstitial Si and vacancies generated upon ion implantation. The generation of the interstitial Si and vacancies is inevitable also in the subsequent ion implantation for forming the deep source and drain regions, and enhanced diffusion in the shallow junction regions is further augmented. The generation of interstitial Si is seen also in a thermal oxidation step, and is called oxidation enhanced diffusion phenomenon, so that it is very difficult to restrain the enhanced diffusion phenomenon in the subsequent steps.
FIG. 3 shows the results of measurement by secondary ion mass spectrometry of impurity distribution in the range from the surface to the inside of a substrate upon ion implantation of boron (B) into an Si single crystal substrate at an acceleration energy of 3 keV and a dose of 1xc3x971015/cm2 and after a short anneal at 1000xc2x0 C. for 10 sec. As is clear from the figure, a tailing phenomenon of the impurity distribution is observed in spite of the low acceleration energy implantation, and it is very difficult to form a shallow junction even with the short period anneal. It is also apparent that impurity concentration gradually and monotonously decreases from the surface toward the depth direction, in other regions than the vicinity of the surface. Namely, the impurity distribution shape obtained at present is far from the rectangular distribution shape with a high concentration of 1020/cm3, which is considered to be an ideal impurity distribution for realizing a low diffusion layer resistance while maintaining a shallow junction.
Therefore, in order to achieve a small size and a larger current with a miniaturized MOS, realization of an optimum impurity distribution offering both shallower junction and lower resistance to the present source and drain junctions is indispensable.
As another phenomenon hampering the provision of source and drain extension junctions with shallow junction and high concentration rectangular distribution, there is known the so-called channeling phenomenon in which implanted ions pass through more than the penetration distance determined by the acceleration energy, because the Si crystal lattice spacing depends on the crystal orientation. In order to prevent the spreading of the impurity concentration distribution due to the channeling phenomenon, there have been known slant angled ion implantation and implantation of a large amount of an ion neutral to Si such as Ge to preliminarily amorphousize the surface region, thereby preventing the channeling phenomenon at the time of ion implantation for forming extension junctions. However, the ion implantation for amorphousizing is also attended by the generation of interstitial Si and vacancies, and it is difficult to realize the formation of an ideal shallow junction. Further, in recrystallization of an amorphousized region by heat treatment, recovery to a perfect crystal is difficult, and a junction formed in the region is affected by crystalline defects nonnegligibly and is attended by generation of junction leakage current.
A technique of using In as a means for preventing the channeling phenomenon is seen in Japanese Patent Laid-Open No. Hei 11-87706. In the publication, the following procedure is adopted: (1) In is implanted though the entire surface of an active region of an N channel MOS transistor (referred to as NMOS) or by using a gate electrode as a mask to achieve amorphousizing; (2) As ion is implanted to form extension junctions; (3) P ion is implanted to form deep source and drain diffusion layers; and (4) heat treatment is carried out for activation of introduced impurities. The purpose of the above technique is to form the deep source and drain diffusion layers to be shallower layers by utilizing the phenomenon of attraction of P by In through setting the implantation penetrate distance of In at a depth between the extension junction and the deep source and drain diffusion layers. Namely, in the above technique, amorphousizing and the phenomenon of attraction of P by In are used for obtaining shallower junctions. Incidentally, according to the description of the above technique, activation coefficient is higher with P than with As, and As is smaller than P in mass; however, this is contrary to the fact, and As ion implantation is ordinarily used also for formation of deep source and drain diffusion layers.
Another technique of applying the phenomenon of mutual attraction of implanted impurities to control of junction is described in Japanese Patent Laid-Open No. Hei 2-114633. In this technique, after Ga is implanted into a surface region, B is implanted with a deeper penetrated distance as compared with Ga, and thereafter heat treatment is carried out to utilize the mutual attraction of Ga and B for forming a shallower P type diffusion layer as compared with the case of singly using B.
A problem to be solved by the present invention is to achieve both shallower junction in source and drain extension junction regions beneath a gate electrode so as to perfectly cut off a source-drain punch-through current path and an impurity distribution capable of extreme reduction of diffusion resistance through a rectangular distribution with a high impurity concentration of not less than 1020/cm3, in obtaining a miniaturized MOS with higher performance, namely, a larger current. Another problem to be solved by the invention is to realize the above impurity distribution structure not only with a P channel MOS transistor (referred to as PMOS) constituted in an N type substrate region but also with a complementary MOS transistor (referred to as CMOS) having an N type region and a P type region in the same semiconductor substrate and having NMOS and PMOS in the N type and P type regions, and to realize an ultra miniaturized MOS capable of providing an ultra miniaturized CMOS with a larger current and higher operation speed.
Incidentally, the term MOS herein is used as an abbreviation for a general insulated gate field effect transistor. Accordingly, in the present invention, the gate insulation film includes not only an oxide film, particularly an Si oxide film, in accordance with the etymology of MOS, but also other films, for example, a nitride film or a composite film of an oxide and other substance.
A further problem to be solved by the invention is to dissolve the disadvantages generated in the prior art of controlling a P diffusion layer by mutual reaction with In. The disadvantages include, for example, bad effects on junction characteristics of amorphousizing or generation of crystal defects by ion implantation of In having a large mass, and an increase of junction leakage current.
Namely, in the prior art, deep source and drain diffusion layers using P are formed so as to outrun an In implanted region, so that the deep source and drain diffusion layers inevitably intersect with the In implanted region at least at a region. Therefore, there has been the difficulty that it is impossible to avoid influence of junction failure at the location of intersection.
A further problem to be solved by the invention is to reduce the junction depth and resistance of extension junction regions most sensitive to realization of a miniaturized MOS with a larger current, as contrasted to the prior art in which the problem is set to be to reduce junction depth of deep source and drain diffusion layers contributing little to realization of a miniaturized MOS with a larger current.
A still further problem to be solved by the invention is to find out an element having the same B-attracting action as Ga and not having the disadvantages of Ga, to realize an extension junction with an extremely steep impurity distribution and low resistance and to thereby achieve a miniaturized MOS with higher performance. The disadvantages of Ga include, for example, (1) that Ga has a small mass and it is difficult to realize a steep distribution in an Si crystal substrate by an ion implantation method, and (2) that Ga is easily diffused outward by an ordinary heat treatment step, and has a high diffusion rate and low activation coefficient, so that it is difficult to obtain a lower resistance and a shallower junction.
Main modes of the present invention will be enumerated as follows.
A first mode of the present invention resides in an insulated gate field effect transistor comprising a PN junction at a portion of a main surface region of a semiconductor substrate of a first conductive type, the PN junction formed by a high concentration impurity region of a second conductive type demarcated by a deep junction and a shallow junction, the high concentration impurity region so constituted as to have a maximum concentration at the surface of the semiconductor substrate, and a second impurity region distributed in the inside of the high concentration region of a first impurity constituting the shallow junction region of the second conductive type, the second impurity region having a maximum concentration in the inside of the semiconductor and having a maximum concentration lower than the maximum impurity concentration of the high concentration region of the first impurity.
The maximum concentration of the first impurity region constituting the shallow junction region is preferably not less than 1xc3x971020 cmxe2x88x923, and the maximum impurity concentration of the second impurity region is preferably not more than 5xc3x971019 cmxe2x88x923.
A second mode of the present invention resides in an insulated gate field effect transistor wherein a first conductive type region and a second conductive type region are provided at main surface portions of the same semiconductor substrate, a first insulated gate field effect transistor comprising a PN junction formed by a high concentration impurity region of a second conductive type demarcated by a deep junction and a shallow junction is provided in the first conductive type region, whereas a second insulated gate field effect transistor comprising a PN junction formed by a high concentration impurity region of a first conductive type demarcated by a deep junction and a shallow junction is provided in the second conductive type region, and a second impurity region having a maximum concentration in the inside of the semiconductor substrate is provided in the high concentration impurity region of the second conductive type constituting the shallow junction and in the high concentration impurity region of the first conductive type. The maximum impurity concentration of the first and second conductive type high concentration impurity regions constituting the shallow junction regions is preferably not less than 1xc3x971020 cmxe2x88x923, and the maximum impurity concentration of the second impurity region is preferably not more than 5xc3x971019 cmxe2x88x923.
A representative example of the impurity constituting the second impurity region is In.
The high concentration impurity regions of the first and second conductive types constituting the shallow junction regions are preferably constituted of As and B.
A third mode of the present invention resides in a method of fabricating an insulated gate field effect transistor comprising the steps of: forming a gate electrode; introducing a first impurity of a second conductive type so as to obtain a maximum impurity concentration at a main surface of a semiconductor substrate by using an end of the gate electrode as an introduction boundary; and introducing a second impurity region of the second conductive type so as to obtain a maximum impurity concentration in the first impurity introduction region in the semiconductor substrate.
A fourth mode of the present invention resides in a method of fabricating an insulated gate field effect transistor, comprising the steps of: forming a gate electrode on a main surface of each of a first conductive type region and a second conductive type region formed in main surface regions of a semiconductor substrate, with a gate insulation film therebetween; selectively introducing a second conductive type high concentration impurity into the first conductive type region and a first conductive type high concentration impurity into the second conductive type region by using each of ends of the gate electrodes as an introduction boundary; and introducing a second conductive type impurity different from the second conductive type high concentration impurity.
Further modes of the present invention will be described in detail below in the description of embodiments of the invention.